International Papers

2024

  • [ASPLOS] Heehoon Kim, Junyeol Ryu, and Jaejin Lee. TCCL: Discovering Better Communication Paths for PCIe GPU Clusters. ASPLOS 2024: Proceedings of the 29th International Conference on Architectural Support for Programming Languages and Operating Systems, Vol. 3, pp. 999-1015, San Diego, USA, April 2024. DOI: 10.1145/3620666.3651362

2023

  • [NeurIPS] Kyusu Ahn, Byeonghyun Ko, HyunGyu Lee, Chanwoo Park, and Jaejin Lee. UDC-SIT: A Real-World Dataset for Under-Display Cameras. NeurIPS 2023: Proceedings of the 37th Conference on Neural Information Processing Systems Datasets and Benchmarks Track, New Orleans, Louisiana, USA, December 2023. DOI: 10.5555/3666122.3669084.
  • [ASPLOS] Jaehoon Jung, Jinpyo Kim, and Jaejin Lee. DeepUM: Tensor Migration and Prefetching in Unified Memory. ASPLOS 2023: Proceedings of the 28th International Conference on Architectural Support for Programming Languages and Operating Systems, Vol. 2, pp. 207-211, Vancouver, Canada, March 2023. DOI: 10.1145/3575693.3575736

2022

  • [ICS] Daeyoung Park, Heehoon Kim, Jinpyo Kim, Taehyun Kim, and Jaejin Lee. SnuQS: Scaling Quantum Circuit Simulation using Storage Sevices. ICS ’22: Proceedings of the 36th ACM International Conference on Supercomputing, No. 6, pp. 1—13, Online, June 2022. DOI: 10.1145/3524059.3532375
  • [ICS] Jinpyo Kim, Hyungdal Kwon, Jintaek Kang, Jihwan Park, Seungwook Lee, and Jaejin Lee. SnuHPL: High Performance LINPACK for Heterogeneous GPUs. ICS ’22: Proceedings of the 36th ACM International Conference on Supercomputing, No. 18, pp. 1—12, Online, June 2022. DOI: 10.1145/3524059.3532370

2021

  • [TPDS] Hyungmin Cho, Jeesoo Lee, and Jaejin Lee. FARNN: FPGA-GPU Hybrid Acceleration Platform for Recurrent Neural Networks. IEEE Transactions on Parallel and Distributed Systems, Vol. 33, No. 7, pp. 1725—1738, November 2021. DOI: 10.1109/TPDS.2021.3124125
  • [MICRO] Jianping Zeng, Hongjune Kim, Jaejin Lee, and Changhee Jung. Turnpike: Lightweight Soft Error Resilience for In-Order Cores. MICRO’21: 54th Annual IEEE/ACM International Symposium on Microarchitecture, pp. 654—666, Online, October 2021. DOI: 10.1145/3466752.3480042
  • [PLDI] Wookeun Jung, Thanh Tuan Dao, and Jaejin Lee. DeepCuts: a deep learning optimization framework for versatile GPU workloads. PLDI ’21: Proceedings of the 42nd ACM SIGPLAN International Conference on Programming Language Design and Implementation, pp. 190—205, Online, June 2021. DOI: 10.1145/3453483.3454038
  • [HPDC] Jaehoon Jung, Daeyoung Park, Gangwon Jo, Jungho Park, and Jaejin Lee. SnuRHAC: A Runtime for Heterogeneous Accelerator Clusters with CUDA Unified Memory. HPDC ’21: Proceedings of the 30th International Symposium on High-Performance Parallel and Distributed Computing, pp. 107—120, Online, June 2021. DOI: 10.1145/3431379.3460647

2020

  • [arXiv] Jinpyo Kim, Wookeun Jung, Hyungmo Kim, and Jaejin Lee. CyCNN: A Rotation Invariant CNN using Polar Mapping and Cylindrical Convolution Layers. July 2020. arXiv: 2007.10588
  • [PLDI] Hongjune Kim, Jianping Zeng, Qingrui Liu, Mohammad Abdel-Majeed, Jaejin Lee, and Changhee Jung. Compiler-Directed Soft Error Resilience for Lightweight GPU Register File Protection. PLDI ’20: Proceedings of the 41th Annual ACM SIGPLAN Conference on Programming Language Design and Implementation, pp. 989—1004, Online, June 2020. DOI: 10.1145/3385412.3386033
  • [ISCA] Gangwon Jo, Heehoon Kim, Jeesoo Lee, and Jaejin Lee. SOFF: An OpenCL High-Level Synthesis Framework for FPGAs. ISCA ’20: Proceedings of the 47th Annual International Symposium on Computer Architecture, pp. 295—308, Online, June 2020. DOI: 10.1109/ISCA45697.2020.00034
  • [PPoPP] Jaehoon Jung, Daeyoung Park, Youngdong Do, Jungho Park, and Jaejin Lee. Overlapping Host-to-Device Copy and Computation using Hidden Unified Memory. PPoPP ’20: Proceedings of the 25th Symposium on Principles and Practice of Parallel Programming, pp. 321—335, San Diego, California, USA, February 2020. DOI: 10.1145/3332466.3374531
  • [IISWC] Youngdong Do, Hyungmo Kim, Pyeongseok Oh, Daeyoung Park, and Jaejin Lee. SNU-NPB 2019: Parallelizing and Optimizing NPB in OpenCL and CUDA for Modern GPUs. IISWC ’19: Proceedings of the 2019 IEEE International Symposium on Workload Characterization, Orlando, Florida, USA, November 2019. DOI: 10.1109/IISWC47752.2019.9041954
  • [ASPLOS] Hyungmin Cho, Pyeongseok Oh, Jiyoung Park, Wookeun Jung, and Jaejin Lee. FA3C: FPGA-Accelerated Deep Reinforcement Learning. ASPLOS ’19: Proceedings of the 24th International Conference on Architectural Support for Programming Languages and Operating Systems, Providence, Rhode Island, USA, April 2019. DOI: 10.1145/3297858.3304058

2018

  • [PPoPP-Poster] Jungho Park, Hyungmin Cho, Wookeun Jung, and Jaejin Lee. Transparent GPU Memory Management for DNNs. PPoPP ’18: Proceedings of the 23rd ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, pp. 411—412, Vienna, Austria, February 2018. DOI: 10.1145/3178487.3178531
  • [TPDS] Thanh Tuan Dao and Jaejin Lee. An Auto-tuner for OpenCL Work-Group Size on GPUs. IEEE Transactions on Parallel and Distributed Systems, Vol. 29, No. 2, pp. 283—296, February 2018. DOI: 10.1109/TPDS.2017.2755657

2017

  • [LCPC] Gangwon Jo, Jaehoon Jung, Jiyoung Park, and Jaejin Lee. Memory-Access-Pattern Analysis Techniques for OpenCL Kernels. LCPC ’17: Proceedings of the 30th International Workshop on Languages and Compilers for Parallel Computing, pp. 109—126, College Station, Texas, USA, October 2017. DOI: 10.1007/978-3-030-35225-7_9
  • [ISPASS] Heehoon Kim, Hyoungwook Nam, Wookeun Jung, and Jaejin Lee. Performance Analysis of CNN Frameworks for GPUs. ISPASS ’17: Proceedings of 2017 IEEE International Symposium on Performance Analysis of Systems and Software, pp. 55—64, Santa Rosa, California, USA, April 2017. DOI: 10.1109/ISPASS.2017.7975270
  • [PPoPP-Poster] Gangwon Jo, Jaehoon Jung, Jiyoung Park, and Jaejin Lee. MAPA: An Automatic Memory Access Pattern Analyzer for GPU Applications. PPoPP ’17: Proceedings of the 22nd ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, pp. 443—444, Austin, Texas, US, February 2017. DOI: 10.1145/3018743.3019034

2016

  • [SC] Junghyun Kim, Yong-Jun Lee, Jungho Park, and Jaejin Lee. Translating OpenMP Device Constructs to OpenCL Using Unnecessary Data Transfer Elimination. SC ’16: Proceedings of the International Conference for High Performance Computing, Networking, Storage and Analysis, No. 51, Salt Lake City, Utah, USA, November 2016. DOI: 10.1109/SC.2016.50
  • [CCS] Jungho Park, Wookeun Jung, Gangwon Jo, Ilkoo Lee, and Jaejin Lee. PIPSEA: A Practical IPsec Gateway on Embedded APUs. CCS ’16: Proceedings of the 2016 ACM SIGSAC Conference on Computer and Communications Security, pp. 1255—1267, Vienna, Austria, October 2016. DOI: 10.1145/2976749.2978329
  • [TC] Bernhard Egger, Eunbyung Park, Younghyun Jo, Changyeon Jo, and Jaejin Lee. Efficient Checkpointing of Live Virtual Machines. IEEE Transactions on Computers, Vol. 65, No. 10, pp. 3041—3054, October 2016. DOI: 10.1109/TC.2016.2519890
  • [BookChapter] Jaejin Lee, Gangwon Jo, Wookeun Jung, Hongjune Kim, Junghyun Kim, Yong-Jun Lee, and Jungho Park. SnuCL: A unified OpenCL framework for heterogeneous clusters. Advances in GPU Research and Practice, pp. 23—56, Morgan Kaufmann, September 2016.
  • [PLDI] Junghyun Kim, Gangwon Jo, Jaehoon Jung, Jungwon Kim, and Jaejin Lee. A Distributed OpenCL Framework using Redundant Computation and Data Replication. PLDI ’16: Proceedings of the 37th Annual ACM SIGPLAN Conference on Programming Language Design and Implementation, pp. 553—569, Santa Barbara, California, USA, June 2016. DOI: 10.1145/2908080.2908094

2015

  • [SC] Junghyun Kim, Thanh Tuan Dao, Jaehoon Jung, Jinyoung Joo, and Jaejin Lee. Bridging OpenCL and CUDA: A Comparative Analysis and Translation. SC ’15: Proceedings of the International Conference for High Performance Computing, Networking, Storage and Analysis, No. 82, Austin, Texas, USA, November 2015. DOI: 10.1145/2807591.2807621
  • [TPDS] Gangwon Jo, Jeongho Nah, Jun Lee, Jungwon Kim, and Jaejin Lee. Accelerating LINPACK with MPI-OpenCL on Clusters of Multi-GPU Nodes. IEEE Transactions on Parallel and Distributed Systems, Vol. 26, No. 7, pp. 1814—1825, July 2015. DOI: 10.1109/TPDS.2014.2321742
  • [TPDS] Thanh Tuan Dao, Jungwon Kim, Sangmin Seo, Bernhard Egger, and Jaejin Lee. A Performance Model for GPUs with Caches. IEEE Transactions on Parallel and Distributed Systems, Vol. 26, No. 7, pp. 1800—1813, July 2015. DOI: 10.1109/TPDS.2014.2333526

2014

  • [PACT] Wookeun Jung, Jongsoo Park, and Jaejin Lee. Versatile and Scalable Parallel Histogram Construction. PACT ’14: Proceedings of the 23rd ACM/IEEE/IFIP International Conference on Parallel Architectures and Compilation Techniques, pp. 127—138, Edmonton, Alberta, Canada, August 2014. DOI: 10.1145/2628071.2628108
  • [LCTES] Hongjune Kim, Seonmyeong Bak, and Jaejin Lee. Lightweight and Block-level Concurrent Sweeping for JavaScript Garbage Collection. LCTES ’14: Proceedings of the 2014 SIGPLAN/SIGBED conference on Languages, compilers and tools for embedded systems, pp. 155—164, Edinburgh, UK, June 2014. DOI: 10.1145/2597809.2597824
  • [WPMVP] Gangwon Jo, Won Jong Jeon, Wookeun Jung, Gordon Taft, and Jaejin Lee. OpenCL Framework for ARM Processors with NEON Support. WPMVP ’14: Proceedings of the 2014 Workshop on Programming Models for SIMD/Vector Processing, pp. 33—40, February 2014. DOI: 10.1145/2568058.2568064

2013

  • [PACT] Sangmin Seo, Jun Lee, Gangwon Jo, and Jaejin Lee. Automatic OpenCL Work-Group Size Selection for Multicore CPUs. PACT ’13: Proceedings of the 22nd ACM/IEEE/IFIP International Conference on Parallel Architectures and Compilation Techniques, pp. 387—397, Edinburgh, Scotland, September 2013. DOI: 10.1109/PACT.2013.6618834
  • [HiPEAC] Choonki Jang, Jaejin Lee, Bernhard Egger, and Soojung Ryu. Automatic Code Overlay Generation and Partially Redundant Code Fetch Elimination. HiPEAC 2013, Berlin, Germany, January 2013.

2012

  • [ICS] Jungwon Kim, Sangmin Seo, Jun Lee, Jeongho Nah, Gangwon Jo, and Jaejin Lee. SnuCL: an OpenCL Framework for Heterogeneous CPU/GPU Clusters. ICS ’12: Proceedings of the 26th International Conference on Supercomputing, pp. 341—352, San Servolo Island, Venice, Italy, June 2012. DOI: 10.1145/2304576.230462
  • [TACO] Choonki Jang, Jaejin Lee, Bernhard Egger, and Soojung Ryu. Automatic Code Overlay Generation and Partially Redundant Code Fetch Elimination. ACM Transactions on Architecture and Code Optimization, Vol. 9, No. 2, June 2012. DOI: 10.1145/2207222.2207226
  • [CGO] Choonki Jang, Jun Lee, Sangmin Seo, and Jaejin Lee.  An Automatic Code Overlaying Technique for Multicores with Explicitly-Managed Memory Hierarchies. CGO ’12: Proceedings of the 2012 International Symposium on Code Generation and Optimization, pp. 219—229, San Jose, California, USA, March 2012. DOI: 10.1145/2259016.2259045
  • [PPoPP-Poster] Jungwon Kim, Sangmin Seo, Jun Lee, Jeongho Nah, Gangwon Jo, and Jaejin Lee. OpenCL as a Unified Programming Model for Heterogeneous CPU/GPU Clusters. PPoPP ’12: Proceedings of the 17th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, pp. 299—300, New Orleans, Louisiana, USA, February 2012. DOI: 10.1145/2145816.2145863

2011

  • [IISWC] Sangmin Seo, Gangwon Jo, and Jaejin Lee. Performance Characterization of the NAS Parallel Benchmarks in OpenCL. IISWC ’11: Proceedings of the 2011 IEEE International Symposium on Workload Characterization, pp. 137—148, Austin, Texas, USA, November 2011. DOI: 10.1109/IISWC.2011.6114174
  • [TECS] Seungkyun Kim, Kiwon Kwon, Chihun Kim, Choonki Jang, Jaejin Lee, and Sang Lyul Min. Demand Paging Techniques for Flash Memory Using Compiler Post-pass Optimizations. ACM Transactions on Embedded Computing Systems, Vol. 10, No. 4, November 2011. DOI: 10.1145/2043662.2043664
  • [PACT] Sangmin Seo, Junghyun Kim, and Jaejin Lee. SFMalloc: A Lock-Free and Mostly Synchronization-Free Dynamic Memory Allocator for Manycores. PACT ’11: Proceedings of the 20th ACM/IEEE/IFIP International Conference on Parallel Architectures and Compilation Techniques, pp. 253—263, Galveston Island, Texas, USA, October 2011. DOI: 10.1109/PACT.2011.57
  • [PACT] Jun Lee, Jungwon Kim, Junghyun Kim, Sangmin Seo, and Jaejin Lee. An OpenCL Framework for Homogeneous Manycores with no Hardware Cache Coherence. PACT ’11: Proceedings of the 20th ACM/IEEE/IFIP International Conference on Parallel Architectures and Compilation Techniques, pp. 56—67, Galveston Island, Texas, USA, October 2011. DOI: 10.1109/PACT.2011.12
  • [PACT-Poster] Jungho Park, Choonki Jang, and Jaejin Lee. A Software-Managed Coherent Memory Architecture for Manycores. PACT ’11: Proceedings of the 20th ACM/IEEE/IFIP International Conference on Parallel Architectures and Compilation Techniques, pp. 213—213, Galveston Island, Texas, USA, October 2011. DOI: 10.1109/PACT.2011.46
  • [LCPC] Jungwon Kim, Sangmin Seo, Jun Lee, Jeongho Nah, Gangwon Jo, and Jaejin Lee. OpenCL as a Programming Model for GPU Clusters. LCPC ’11: Proceedings of the 24th International Workshop on Languages and Compilers for Parallel Computing, pp. 76—90, Fort Collins, Colorado, USA, September 2011. DOI: 10.1007/978-3-642-36036-7_6
  • [APSys] Junghyun Kim, Sangmin Seo, and Jaejin Lee. An Efficient Software Shared Virtual Memory for the Single-chip Cloud Computer. APSys ’11: Proceedings of the 2nd ACM SIGOPS Asia-Pacific Workshop on Systems, No. 4, Shanghai, China, July 2011. DOI: 10.1145/2103799.2103804
  • [ICS-Poster] Choonki Jang. SRC: An Automatic Code Overlaying Technique for Multicores with Explicitly-Managed Memory Hierarchies. ICS ’11: Proceedings of the 25th ACM International Conference on Supercomputing, pp. 377—377, Tucson, Arizona, USA, June 2011. DOI: 10.1145/1995896.1995960
  • [LCTES] Choonki Jang, Jungwon Kim, Jaejin Lee, Hee-Seok Kim, Dong-Hoon Yoo, Sukjin Kim, Hong-Seok Kim, and Soojung Ryu. An Instruction-Scheduling-Aware Data Partitioning Technique for Coarse-Grained Reconfigurable Architectures. LCTES ’11: Proceedings of the ACM SIGPLAN/SIGBED 2011 International Conference on Languages, Compilers, and Tools for Embedded Systems, pp. 151—160, Chicago, Illinois, USA, April 2011. DOI: 10.1145/1967677.1967699
  • [VEE] Eunbyung Park, Bernhard Egger, and Jaejin Lee. Fast and Space Efficient Virtual Machine Checkpointing. VEE ’11: Proceedings of the 2011 ACM SIGPLAN/SIGOPS International Conference on Virtual Execution Environments, pp. 75—85, Newport Beach, California, USA, March 2011. DOI: 10.1145/1952682.1952694
  • [PPoPP] Jungwon Kim, Honggyu Kim, Joo Hwan Lee, and Jaejin Lee. Achieving a Single Compute Device Image in OpenCL for Multiple GPUs. PPoPP ’11: Proceedings of the 16th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, pp. 277—288, San Antonio, Texas, USA, February 2011. DOI: 10.1145/1941553.1941591

2010

  • [EMSoft] Yongjin Cho, Seungkyun Kim, Jaejin Lee, and Heonshik Shin. Parallelizing the H.264 Decoder on the Cell BE Processor. EMSoft ’10: Proceedings of the 10th ACM International Conference on Embedded Software, pp. 49—58, Scottsdale, Arizona, USA, October 2010. DOI: 10.1145/1879021.1879029
  • [PACT] Jaejin Lee, Jungwon Kim, Sangmin Seo, Seungkyun Kim, Jungho Park, Honggyu Kim, Thanh Tuan Dao, Yongjin Cho, Sung Jong Seo, Seung Hak Lee, Seung Mo Cho, Hyo Jung Song, Sang-Bum Suh, and Jong-Deok Choi. An OpenCL Framework for Heterogeneous Multicores with Local Memory. PACT ’10: Proceedings of the 19th ACM/IEEE/IFIP International Conference on Parallel Architectures and Compilation Techniques, pp. 193—204, Vienna, Austria, September 2010. DOI: 10.1145/1854273.1854301
  • [PACT-Poster] Jun Lee, Sangmin Seo, and Jaejin Lee. A Software-SVM-based Transactional Memory for Multicore Accelerator Architectures with Local Memory. PACT ’10: Proceedings of the 19th ACM/IEEE/IFIP International Conference on Parallel Architectures and Compilation Techniques, pp. 567—568, Vienna, Austria, September 2010. DOI: 10.1145/1854273.1854355
  • [TC] Bernhard Egger, Seungkyun Kim, Choonki Jang, Jaejin Lee, Sang Lyul Min, and Heonshik Shin. Scratchpad Memory Management Techniques for Code in Embedded Systems without an MMU. IEEE Transactions on Computers, Vol. 59, No. 8, pp. 1047—1062, August 2010. DOI: 10.1109/TC.2009.188
  • [TC] Yoon Jae Seong, Eyee Hyun Nam, Jin Hyuk Yoon, Hongseok Kim, Jin-yong Choi, Sookwan Lee, Young Hyun Bae, Jaejin Lee, Yookun Cho, and Sang Lyul Min. Hydra: A Block-Mapped Parallel Flash Memory Solid State Disk Architecture. IEEE Transactions on Computers, Vol. 59, No. 7, pp. 905—921, July 2010. DOI: 10.1109/TC.2010.63
  • [JPDC] Jaejin Lee, Jung-Ho Park, Honggyu Kim, Changhee Jung, Daeseob Lim, and SangYong Han. Adaptive Execution Techniques of Parallel Programs for Multiprocessors. Journal of Parallel and Distributed Computing, Vol. 70, No. 5, pp. 467—480, May 2010. DOI: 10.1016/j.jpdc.2009.10.008
  • [HPCA] Jaejin Lee, Jun Lee, Sangmin Seo, Jungwon Kim, Seungkyun Kim, and Zehra Sura. COMIC++: A Software SVM System for Heterogeneous Multicore Accelerator Clusters. HPCA ’10: Proceedings of the 16th IEEE International Symposium on High Performance Computer Architecture, pp. 329—340, Bangalore, India, January 2010. DOI: 10.1109/HPCA.2010.5416633

2009

  • [TPDS] Jaejin Lee, Changhee Jung, Daeseob Lim, and Yan Solihin. Prefetching with Helper Threads for Loosely-Coupled Multiprocessor Systems. IEEE Transactions on Parallel and Distributed Systems, Vol. 20, No. 9, pp. 1309—1324, September 2009. DOI: 10.1109/TPDS.2008.224
  • [HPCA] Sangmin Seo, Jaejin Lee, and Zehra Sura. Design and Implementation of Software-Managed Caches for Multicores with Local Memory. HPCA ’09: Proceedings of the 15th IEEE International Symposium on High Performance Computer Architecture, pp. 55—66, Raleigh, North Carolina, USA, February 2009. DOI: 10.1109/HPCA.2009.4798237

2008

  • [PACT] Jaejin Lee, Sangmin Seo, Chihun Kim, Junghyun Kim, Posung Chun, Zehra Sura, Jungwon Kim, and SangYong Han. COMIC: A Coherent Shared Memory Interface for Cell BE. PACT ’08: Proceedings of the 17th ACM/IEEE/IFIP International Conference on Parallel Architectures and Compilation Techniques, pp. 303—314, Toronto, Canada, October 2008. DOI: 10.1145/1454115.1454157
  • [EMSoft] Bernhard Egger, Jaejin Lee, and Heonshik Shin. Scratchpad Memory Management in a Multitasking Environment. EMSoft ’08: Proceedings of the 8th ACM International Conference on Embedded Software, pp. 265—274, Atlanta, Georgia, October 2008. DOI: 10.1145/1450058.1450094
  • [JCSE] Jongsoo Park and Jaejin Lee. A Practical Improvement to the Partial Redundancy Elimination in SSA Form. Journal of Computing Science and Engineering, Vol. 2, No. 3, pp. 301—320, September 2008. DOI: 10.5626/JCSE.2008.2.3.301
  • [LCTES] Jaejin Lee, Junghyun Kim, Choonki Jang, Seungkyun Kim, Bernhard Egger, Kwangsub Kim, and SangYong Han. FaCSim: A Fast and Cycle-Accurate Architecture Simulator for Embedded Systems. LCTES ’08: Proceedings of the ACM SIGPLAN/SIGBED 2008 International Conference on Languages, Compilers, and Tools for Embedded Systems, pp. 89—99, Tucson, Arizona, USA, June 2008. DOI: 10.1145/1379023.1375670
  • [TECS] Bernhard Egger, Jaejin Lee, and Heonshik Shin. Dynamic Scratchpad Memory Management for Code in Portable Systems with an MMU. ACM Transactions on Embedded Computing Systems, Vol. 7, No. 2, February 2008. DOI: 10.1145/1331331.1331335

2007

  • [LCTES] Hyeongmin Cho, Bernhard Egger, Jaejin Lee, and Heonshik Shin. Dynamic Data Scratchpad Memory Management for a Memory Subsystem with an MMU. LCTES ’07: Proceedings of the ACM SIGPLAN/SIGBED 2007 International Conference on Languages, Compilers, and Tools for Embedded Systems, pp. 195—206, San Diego, California, USA, June 2007. DOI: 10.1145/1273444.1254804
  • [TECS] Sheayun Lee, Jaejin Lee, Chang Yun Park, and Sang Lyul Min. Selective Code Transformation for Dual Instruction Set Processors. ACM Transactions on Embedded Computing Systems, Vol. 6, No. 2, May 2007. DOI: 10.1145/1234675.1234677

2006

  • [EMSoft] Bernhard Egger, Jaejin Lee, and Heonshik Shin. Scratchpad Memory Management for Portable Systems with a Memory Management Unit. EMSoft ’06: Proceedings of the 6th ACM International Conference on Embedded Software, pp. 321—330, Seoul, Korea, October 2006. DOI: 10.1145/1176887.1176933
  • [CASES] Bernhard Egger, Chihun Kim, Choonki Jang, Yoonsung Nam, Jaejin Lee, and Sang Lyul Min. A Dynamic Code Placement Technique for Scratchpad Memory using Postpass Optimization. CASES ’06: Proceedings of the 2006 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, pp. 223—233, Seoul, Korea, October 2006. DOI: 10.1145/1176760.1176788
  • [IPDPS] Changhee Jung, Daesub Lim, Jaejin Lee, and Yan Solihin. Helper Thread Prefetching for Loosely-Coupled Multiprocessor Systems. IPDPS ’06: Proceedings of the 2006 IEEE International Parallel & Distributed Processing Symposium, pp. 118—127, Rhodes Island, Greece, April 2006. DOI: 10.1109/IPDPS.2006.1639375

2005

  • [LCPC] Chi-Leung Wong, Zehra Sura, Xing Fang, Kyungwoo Lee, Samuel P. Midkiff, Jaejin Lee, and David Padua. Evaluating the Impact of Thread Escape Analysis on a Memory Consistency Model-Aware Compiler. LCPC ’05: Proceedings of the 18th International Workshop on Languages and Compilers for Parallel Computing, pp. 170—184, Hawthorne, New York, October 2005. DOI: 10.1007/978-3-540-69330-7_12
  • [PPoPP] Zehra Sura, Xing Fang, Chi-Leung Wong, Samuel P. Midkiff, Jaejin Lee, and David Padua. Techniques for High Performance Sequentially Consistent Java Programs. PPoPP ’05: Proceedings of the ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, pp. 2—13, Chicago, Illinois, USA, June 2005. DOI: 10.1145/1065944.1065947
  • [PPoPP] Changhee Jung, Daeseob Lim, Jaejin Lee, and SangYong Han. Adaptive Execution Techniques for SMT Multiprocessor Architectures. PPoPP ’05: Proceedings of the ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, pp. 236—246, Chicago, Illinois, USA, June 2005. DOI: 10.1145/1065944.1065976
  • [TC] Mazen Kharbutli, Yan Solihin, and Jaejin Lee. Eliminating Conflict Misses Using Prime Number-Based Cache Indexing. IEEE Transactions on Computers, Vol. 54, No. 5, pp. 573—586, May 2005. DOI: 10.1109/TC.2005.79

2004

  • [EMSoft] Chanik Park, Junghee Lim, Kiwon Kwon, Jaejin Lee, and Sang Lyul Min. Compiler Assisted Demand Paging for Embedded Systems with Flash Memory. EMSoft ’04: Proceedings of the 4th ACM International Conference on Embedded Software, pp. 114—124, Pisa, Italy, September 2004. DOI: 10.1145/1017753.1017775
  • [PARC] Bernhard Egger, Jaejin Lee, and Heonshik Shin. An Application-Specific and Adaptive Power Management Technique. PARC ’04: Proceedings of the First International Workshop on Power-Aware Real-Time Computing, Pisa, Italy, September 2004.
  • [SCOPE] Sheayun Lee, Jaejin Lee, Chang Yun Park, and Sang Lyul Min. Flexible Tradeoff between Code Size and WCET Using a Dual Instruction Set Processor. SCOPE ’04: Proceedings of the 8th International Workshop on Software and Compilers for Embedded Systems, pp. 244—258, Amsterdam, Netherlands, September 2004. DOI: 10.1007/b99901
  • [HPCA] Mazen Kharbutli, Yan Solihin, and Jaejin Lee. Using Prime Numbers for Cache Indexing to Eliminate Conflict Misses. HPCA ’04: Proceedings of the 10th International Symposium on High Performance Computer Architecture, pp. 288—299, Madrid, Spain, February 2004. DOI: 10.1109/HPCA.2004.10015
  • [CPE] Samuel P. Midkiff, Jaejin Lee, and David A. Padua. A Compiler for Multiple Memory Models. Concurrency and Computation: Practice and Experience: Special Issue on Compilers for Parallel Computers, Vol. 16, No. 03-2, pp. 197—220, February 2004. DOI: 10.1002/cpe.771

2003

  • [SCOPE] Sheayun Lee, Jaejin Lee, Sang Lyul Min, Jason Hiser, and Jack W. Davidson. Code Generation for a Dual Instruction Set Processor Based on Selective Code Transformation. SCOPE ’03: Proceedings of the 7th International Workshop on Software and Compilers for Embedded Systems, pp. 33—48, Vienna, Austria, September 2003. DOI: 10.1007/b13482
  • [WCET] Sheayun Lee, Jaejin Lee, Chang Yun Park, and Sang Lyul Min. A Flexible Tradeoff between Code Size and WCET Employing Dual Instruction Set Processors. WCET ’03: Proceedings of the 3rd International Workshop on Worst-Case Execution Time Analysis, pp. 91—94, Porto, Portugal, July 2003.
  • [ICS] Xing Fang, Jaejin Lee, and Samuel P. Midkiff. Automatic Fence Insertion for Shared Memory Multiprocessing. ICS ’03: Proceedings of the 17th ACM International Conference on Supercomputing, pp. 285—294, San Francisco, Bay Area, USA, June 2003. DOI: 10.1145/782814.782854
  • [TPDS] Yan Solihin, Jaejin Lee, and Josep Torrellas. Correlation Prefetching with a User Level Memory Thread. IEEE Transactions on Parallel and Distributed Systems, Vol. 14, No. 6, pp. 563—580, June 2003. DOI: 10.1109/TPDS.2003.1206504

2002

  • [LCPC] Jaejin Lee and H. D. K. Moonesinghe. Adaptively Increasing Performance and Scalability of Automatically Parallelized Programs. LCPC ’02: Proceedings of the 15th International Workshop on Languages and Compilers for Parallel Computing, pp. 203—217, College Park, Maryland, USA, July 2002. DOI: 10.1007/11596110_14
  • [LCPC] Zehra Sura, Chi-Leung Wong, Xing Fang, Jaejin Lee, Samuel P. Midkiff, and David Padua. Automatic Implementation of Programming Language Consistency Models. LCPC ’02: Proceedings of the 15th International Workshop on Languages and Compilers for Parallel Computing, pp. 172—187, College Park, Maryland, USA, July 2002. DOI: 10.1007/11596110_12
  • [LCPC] Ji Zhang, Jaejin Lee, and Philip K. McKinley. Optimizing the Java Pipe I/O Stream Library for Performance. LCPC ’02: Proceedings of the 15th International Workshop on Languages and Compilers for Parallel Computing, pp. 233—248, College Park, Maryland, USA, July 2002. DOI: 10.1007/11596110_16
  • [ISPAN] Chi-Leung Wong, Zehra Sura, Xing Fang, Samuel P. Midkiff, Jaejin Lee, and David Padua. The Pensieve Project: A Compiler Infrastructure for Memory Models. ISPAN ’02: Proceedings of the 6th International Symposium on Parallel Architectures, Algorithms, and Networks, pp. 239—244, Manila, Philippines, May 2002. DOI: 10.1109/ISPAN.2002.1004288
  • [ISCA] Yan Solihin, Jaejin Lee, and Josep Torrellas. Using a User-Level Memory Thread for Correlation Prefetching. Using a User-Level Memory Thread for Correlation Prefetching. ISCA ’02: Proceedings of the 29th Annual International Symposium on Computer Architecture, pp. 171—182, Anchorage, Alaska, USA, May 2002. DOI: 10.1109/ISCA.2002.1003576

2001

  • [MTEAC] Yan Solihin, Jaejin Lee, and Josep Torrellas. Prefetching in an Intelligent Memory Architecture Using a Helper Thread. MTEAC-5: Proceedings of the 5th Workshop on Multithreaded Execution, Architecture and Compilation, Austin, Texas, USA, December 2001.
  • [TC] Yan Solihin, Jaejin Lee, and Josep Torrellas. Automatic Code Mapping on an Intelligent Memory Architecture. IEEE Transactions on Computers: Special Issue on Advances in High Performance Memory Systems, Vol. 50, No. 11, pp. 1248—1266, November 2001. DOI: 10.1109/12.966498
  • [TC] Jaejin Lee and David A. Padua. Hiding Relaxed Memory Consistency with a Compiler. IEEE Transactions on Computers: Special Issue on Parallel Architectures and Compilation Techniques, Vol. 50, No. 8, pp. 824—833, August 2001. DOI: 10.1109/12.947002
  • [CPC] Samuel P. Midkiff, Jaejin Lee, and David A. Padua. A Compiler for Multiple Memory Models. CPC ’01: Proceedings of the 9th Workshop on Compilers for Parallel Computers, Edinburgh, Scotland, UK, June 2001.
  • [TR] Jaejin Lee and David A. Padua. A Compiler Technique to Hide Relaxed Memory Consistency. Technical Report MSU-CSE-01-13, Department of Computer Science and Engineering, Michigan State University, Michigan, USA, April 2001.
  • [TR] Jaejin Lee, David A. Padua, and Samuel P. Midkiff. Basic Compilation Techniques for Explicitly Parallel Programs. Technical Report MSU-CSE-01-14, Department of Computer Science and Engineering, Michigan State University, Michigan, USA, April 2001.
  • [HPCA] Jaejin Lee, Yan Solihin, and Josep Torrellas. Automatically Mapping Code on an Intelligent Memory Architecture. HPCA ’01: Proceedings of the 7th International Symposium on High Performance Computer Architecture, pp. 121—132, Monterrey, Mexico, January 2001. DOI: 10.1109/HPCA.2001.903257

2000

  • [TR] Jaejin Lee. Hiding the Java Memory Model with Compilers. Technical Report MSU-CSE-00-29, Department of Computer Science and Engineering, Michigan State University, Michigan, USA, December 2000.
  • [IMS] Yan Solihin, Jaejin Lee, and Josep Torrellas. Adaptively Mapping Code in an Intelligent Memory Architecture. IMS ’00: Proceedings of the 2nd Workshop on Intelligent Memory Systems, pp. 71—84, Cambridge, Massachusetts, USA, November 2000. DOI: 10.1007/3-540-44570-6_5
  • [PACT] Jaejin Lee and David A. Padua. Hiding Relaxed Memory Consistency with Compilers. PACT ’00: Proceedings of the 9th International Conference on Parallel Architectures and Compilation Techniques, pp. 111—122, Philadelphia, Pennsylvania, October 2000. DOI: 10.1109/PACT.2000.888336
  • [PPoPP] Jaejin Lee, David A. Padua, and Samuel P. Midkiff. Basic Compiler Algorithms for Parallel Programs. PPoPP ’99: Proceedings of the 7th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, pp. 1—12, Atlanta, Georgia, USA, May 1999. DOI: 10.1145/329366.301105

1998

  • [IJPP] Jaejin Lee, Samuel P. Midkiff, and David A. Padua. A Constant Propagation Algorithm for Explicitly Parallel Programs. International Journal of Parallel Programming, Vol. 26, No. 5, pp. 563—589, October 1998. DOI: 10.1023/A:1018772514882

1997

  • [LCPC] Jaejin Lee, Samuel P. Midkiff, and David A. Padua. Concurrent Static Single Assignment Form and Constant Propagation for Explicitly Parallel Programs. LCPC ’97: Proceedings of the 10th International Workshop on Languages and Compilers for Parallel Computing, pp. 114—130, Twin Cities, Minnesota, August 1997. DOI: 10.1007/BFb0032687
  • [TR] Jaejin Lee, Samuel P. Midkiff, and David A. Padua. Concurrent Static Single Assignment Form and Concurrent Sparse Conditional Constant Propagation for Explicitly Parallel Programs. Technical Report TR1525, Center for Supercomputing Research and Development, University of Illinois at Urbana-Champaign, Illinois, USA, July 1997.
  • [INTERACT] Jaejin Lee and David A. Padua. Parallel Static Single Assignment Form and Constant Propagation for Explicitly Parallel Programs. INTERACT-2: Proceedings of the 2nd Workshop on Interaction between Compilers and Computer Architectures, San Antonio, Texas, February 1997.

1996

  • [COMPUTER] William Blume, Ramon Doallo, Rudolf Eigenmann, John Grout, Jay Hoeflinger, Thomas Lawrence, Jaejin Lee, David Padua, Yunheung Paek, Bill Pottenger, Lawrence Rauchwerger, and Peng Tu. Parallel Programming with Polaris. IEEE Computer, Vol. 29, No. 12, pp. 78—82, December 1996. DOI: 10.1109/2.546612
  • [WCPP] William Blume, Rudolf Eigenman, K. Faigin, John Grout, Thomas Lawrence, Jaejin Lee, Jay Hoeflinger, David Padua, Yunheung Paek, Paul Petersen, William Pottenger, Lawrence Rauchwerger, Stephen Weatherford, and Peng Tu. Restructuring Programs for High-Speed Computers with Polaris. Proceedings of the 1996 Workshop on Challenges for Parallel Processing, August 1996.
  • [TR] William Blume, Rudolf Eigenman, K. Faigin, John Grout, Thomas Lawrence, Jaejin Lee, Jay Hoeflinger, David Padua, Yunheung Paek, Paul Petersen, William Pottenger, Lawrence Rauchwerger, Stephen Weatherford, and Peng Tu. Advanced Program Restructuring for High-Performance Computers with Polaris. Technical Report TR1473, Center for Supercomputing Research and Development, University of Illinois at Urbana-Champaign, Illinois, USA, January 1996.

1995

  • [TAPSOFT] Zohar Manna, Nikolaj Bjorner, Anca Browne, Edward Chang, Michael Colon, Luca de Alfaro, Harish Devarajan, Arjun Kapur, Jaejin Lee, Henny Sipma, and Tomas E. Uribe. STeP: The Stanford Temporal Prover. Proceedings of TAPSOFT ’95: Theory and Practice of Software Development, 6th International Joint Conference CAAP/FASE, pp. 793—794, May 1995.